(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device having copper wiring.
(b) Description of the Related Art
In many general logic devices, copper wiring may be more widely used than aluminum lines, which have a drawback in RC delay. Unlike aluminum wiring, copper wiring is formed by a process including steps of forming an insulation layer pattern by a damascene process and forming a copper layer thereon by an electroplating process.
FIGS. 1 to 4 are cross-sectional views showing sequential stages of a conventional method for manufacturing a semiconductor device having copper wiring.
Referring to FIG. 1, a transistor is formed on a silicon substrate 10. The transistor may include a trench oxide layer 11 for isolating an active region of the silicon substrate 10, a gate oxide layer (not shown) formed in the active region, a gate stack 16 comprising a polysilicon layer 12 and a metal silicide layer 14, a gate spacer 18 formed on sidewalls of the gate stack 16, and source/drain terminals 20 formed in alignment with the gate stack 16. The gate spacer 18 may include layers 18a, 18b, and 18c including oxide and nitride layers. In addition, a metal silicide layer 22 may be also formed on a surface of the source/drain terminals 20.
After forming a thin layer 24 on the entire surface of the transistor, a first insulation layer 26 is formed on the liner layer 24. A contact hole 28 is formed by selectively etching the first insulation layer 26 over the source/drain terminals 20 (and, generally, over the gate 16). After forming a first barrier metal layer 29 in the contact hole 28, a tungsten plug 30 is formed on the first barrier metal layer 29 so as to fill the contact hole 28. The tungsten plug 30 is formed by filing the contact hole 28 with a tungsten layer and planarizing by a chemical mechanical polishing (CMP) process.
Referring to FIG. 2, after a second insulation layer 31 is formed on the tungsten plug 30, a trench 32 may be formed by selectively etching the second insulation layer 31 by photolithography and etching to expose an upper surface of the tungsten plug 30.
Subsequently, referring to FIG. 3, a second barrier metal layer 34 is formed on an interior wall of the trench 32. Then, a copper seed layer 36 is formed on the second barrier metal layer 34.
Referring to FIG. 4, a copper line layer 38 is formed on the copper seed layer 36 so as to fill the trench 32. The copper seed layer 36 included in the copper line layer 38 is omitted in FIG. 4.
According to the conventional method for manufacturing a semiconductor device having copper wiring, even if a cleaning process follows chemical mechanical polishing of the tungsten layer of FIG. 1, residues included in slurry used in the chemical mechanical polishing process may remain on the surface of the device so as to cause a device failure. In addition, even if the tungsten layer is removed by chemical mechanical polishing, residue of the tungsten layer may remain on the surface of the insulation layer 26.
Furthermore, by-products (for example, polymers formed during the etching process for the trench in FIG. 2) may remain on a sidewall of the trench or on the tungsten plug, and these by-products may act as an insulation layer or a resistor (e.g., in the case of a very thin layer of such a by-product). The by-products cause the tungsten plug to be electrically insulated from the second barrier metal layer and the copper line layer, or could cause an unacceptable or undesirable increase in the resistivity of the tungsten plug. As a result, the semiconductor device manufactured by the conventional method may not work, or its reliability may be deteriorated.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not form prior art or other information that is already known in this or any other country to a person of ordinary skill in the art.